From f1e0730701e6bf2ece78f50c24bf0a5dad41b604 Mon Sep 17 00:00:00 2001 From: Wulfsta Date: Fri, 4 Apr 2025 18:18:29 -0400 Subject: lis3dh: increase scale from 8g to 16g Signed-off-by: Luke Vuksta --- klippy/extras/lis2dw.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'klippy') diff --git a/klippy/extras/lis2dw.py b/klippy/extras/lis2dw.py index ce453f63..d276c2f8 100644 --- a/klippy/extras/lis2dw.py +++ b/klippy/extras/lis2dw.py @@ -34,7 +34,7 @@ LIS_I2C_ADDR = 0x19 # Right shift for left justified registers. FREEFALL_ACCEL = 9.80665 LIS2DW_SCALE = FREEFALL_ACCEL * 1.952 / 4 -LIS3DH_SCALE = FREEFALL_ACCEL * 3.906 / 16 +LIS3DH_SCALE = FREEFALL_ACCEL * 11.718 / 16 BATCH_UPDATES = 0.100 @@ -167,8 +167,8 @@ class LIS2DW: self.set_reg(REG_LIS2DW_CTRL_REG1_ADDR, 0x97) # Disable all filtering self.set_reg(REG_LIS2DW_CTRL_REG2_ADDR, 0) - # Set +-8g, High Resolution mode - self.set_reg(REG_LIS2DW_CTRL_REG4_ADDR, 0x28) + # Set +-16g, High Resolution mode + self.set_reg(REG_LIS2DW_CTRL_REG4_ADDR, 0x38) # Enable FIFO self.set_reg(REG_LIS2DW_CTRL_REG5_ADDR, 0x40) # Stream mode -- cgit v1.2.3-70-g09d2