From a65e04aff7720fa1ac8e0967c2d71736911a8112 Mon Sep 17 00:00:00 2001 From: D4SK Date: Thu, 20 Oct 2022 22:10:36 +0200 Subject: docs: Add step rate benchmark for stm32h7 Signed-off-by: Konstantin Vogel Signed-off-by: Kevin O'Connor --- docs/Benchmarks.md | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'docs/Benchmarks.md') diff --git a/docs/Benchmarks.md b/docs/Benchmarks.md index ff2b895c..f9d0c92b 100644 --- a/docs/Benchmarks.md +++ b/docs/Benchmarks.md @@ -248,6 +248,26 @@ results were obtained by running an STM32F407 binary on an STM32F446 | 1 stepper | 46 | | 3 stepper | 205 | +### STM32H7 step rate benchmark + +The following configuration sequence is used on a STM32H743VIT6: +``` +allocate_oids count=3 +config_stepper oid=0 step_pin=PD4 dir_pin=PD3 invert_step=-1 step_pulse_ticks=0 +config_stepper oid=1 step_pin=PA15 dir_pin=PA8 invert_step=-1 step_pulse_ticks=0 +config_stepper oid=2 step_pin=PE2 dir_pin=PE3 invert_step=-1 step_pulse_ticks=0 +finalize_config crc=0 +``` + +The test was last run on commit `00191b5c` with gcc version +`arm-none-eabi-gcc (15:8-2019-q3-1+b1) 8.3.1 20190703 (release) +[gcc-8-branch revision 273027]`. + +| stm32h7 | ticks | +| -------------------- | ----- | +| 1 stepper | 44 | +| 3 stepper | 198 | + ### STM32G0B1 step rate benchmark The following configuration sequence is used on the STM32G0B1: -- cgit v1.2.3-70-g09d2