diff options
Diffstat (limited to 'src/stm32/stm32h7.c')
| -rw-r--r-- | src/stm32/stm32h7.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/stm32/stm32h7.c b/src/stm32/stm32h7.c index f58154d7..c6c057d2 100644 --- a/src/stm32/stm32h7.c +++ b/src/stm32/stm32h7.c @@ -5,7 +5,7 @@ // This file may be distributed under the terms of the GNU GPLv3 license. -// USB and I2C is not supported, SPI is untested! +// I2C is not supported #include "autoconf.h" // CONFIG_CLOCK_REF_FREQ #include "board/armcm_boot.h" // VectorTable @@ -170,7 +170,10 @@ clock_setup(void) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE_Msk, RCC_PLLCFGR_PLL1RGE_2); // Disable unused PLL1 outputs MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN_Msk, 0); - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN_Msk, 0); + // Enable PLL1Q and set to 100MHz for SPI 1,2,3 + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN, RCC_PLLCFGR_DIVQ1EN); + MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1, + (pll_freq / FREQ_PERIPH - 1) << RCC_PLL1DIVR_Q1_Pos); // This is necessary, default is not 1! MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN_Msk, RCC_PLLCFGR_DIVP1EN); // Set multiplier DIVN1 and post divider DIVP1 @@ -184,6 +187,7 @@ clock_setup(void) MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS_Msk, PWR_D3CR_VOS); while (!(PWR->D3CR & PWR_D3CR_VOSRDY)) ; + // Enable VOS0 (overdrive) if (CONFIG_CLOCK_FREQ > 400000000) { RCC->APB4ENR |= RCC_APB4ENR_SYSCFGEN; |