aboutsummaryrefslogtreecommitdiffstats
path: root/src/stm32/stm32f0_serial.c
diff options
context:
space:
mode:
Diffstat (limited to 'src/stm32/stm32f0_serial.c')
-rw-r--r--src/stm32/stm32f0_serial.c69
1 files changed, 69 insertions, 0 deletions
diff --git a/src/stm32/stm32f0_serial.c b/src/stm32/stm32f0_serial.c
new file mode 100644
index 00000000..ce9e3c1d
--- /dev/null
+++ b/src/stm32/stm32f0_serial.c
@@ -0,0 +1,69 @@
+// STM32F0 serial
+//
+// Copyright (C) 2019 Kevin O'Connor <kevin@koconnor.net>
+//
+// This file may be distributed under the terms of the GNU GPLv3 license.
+
+#include "autoconf.h" // CONFIG_SERIAL_BAUD
+#include "board/armcm_boot.h" // armcm_enable_irq
+#include "board/serial_irq.h" // serial_rx_byte
+#include "command.h" // DECL_CONSTANT_STR
+#include "internal.h" // enable_pclock
+#include "sched.h" // DECL_INIT
+
+// Select the configured serial port
+#if CONFIG_SERIAL_PORT == 1
+DECL_CONSTANT_STR("RESERVE_PINS_serial", "PA10,PA9");
+#define GPIO_Rx GPIO('A', 10)
+#define GPIO_Tx GPIO('A', 9)
+#define USARTx USART1
+#define USARTx_IRQn USART1_IRQn
+#elif CONFIG_SERIAL_PORT == 2
+DECL_CONSTANT_STR("RESERVE_PINS_serial", "PA3,PA2");
+#define GPIO_Rx GPIO('A', 3)
+#define GPIO_Tx GPIO('A', 2)
+#define USARTx USART2
+#define USARTx_IRQn USART2_IRQn
+#endif
+
+#define CR1_FLAGS (USART_CR1_UE | USART_CR1_RE | USART_CR1_TE \
+ | USART_CR1_RXNEIE)
+
+void
+USARTx_IRQHandler(void)
+{
+ uint32_t sr = USARTx->ISR;
+ if (sr & (USART_ISR_RXNE | USART_ISR_ORE))
+ serial_rx_byte(USARTx->RDR);
+ if (sr & USART_ISR_TXE && USARTx->CR1 & USART_CR1_TXEIE) {
+ uint8_t data;
+ int ret = serial_get_tx_byte(&data);
+ if (ret)
+ USARTx->CR1 = CR1_FLAGS;
+ else
+ USARTx->TDR = data;
+ }
+}
+
+void
+serial_enable_tx_irq(void)
+{
+ USARTx->CR1 = CR1_FLAGS | USART_CR1_TXEIE;
+}
+
+void
+serial_init(void)
+{
+ enable_pclock((uint32_t)USARTx);
+
+ uint32_t pclk = get_pclock_frequency((uint32_t)USARTx);
+ uint32_t div = DIV_ROUND_CLOSEST(pclk, CONFIG_SERIAL_BAUD);
+ USARTx->BRR = (((div / 16) << USART_BRR_DIV_MANTISSA_Pos)
+ | ((div % 16) << USART_BRR_DIV_FRACTION_Pos));
+ USARTx->CR1 = CR1_FLAGS;
+ armcm_enable_irq(USARTx_IRQHandler, USARTx_IRQn, 0);
+
+ gpio_peripheral(GPIO_Rx, GPIO_FUNCTION(1), 1);
+ gpio_peripheral(GPIO_Tx, GPIO_FUNCTION(1), 0);
+}
+DECL_INIT(serial_init);