diff options
| -rw-r--r-- | src/stm32/stm32f0.c | 4 | ||||
| -rw-r--r-- | src/stm32/stm32f1.c | 11 | ||||
| -rw-r--r-- | src/stm32/stm32f4.c | 4 | ||||
| -rw-r--r-- | src/stm32/stm32h7.c | 4 |
4 files changed, 15 insertions, 8 deletions
diff --git a/src/stm32/stm32f0.c b/src/stm32/stm32f0.c index a2a3a52f..06b5d3ab 100644 --- a/src/stm32/stm32f0.c +++ b/src/stm32/stm32f0.c @@ -64,6 +64,8 @@ gpio_clock_enable(GPIO_TypeDef *regs) RCC->AHBENR; } +#define STM_OSPEED 0x2 // ~2Mhz at 50pF + // Set the mode and extended function of a pin void gpio_peripheral(uint32_t gpio, uint32_t mode, int pullup) @@ -84,7 +86,7 @@ gpio_peripheral(uint32_t gpio, uint32_t mode, int pullup) regs->MODER = (regs->MODER & ~m_msk) | (mode_bits << m_shift); regs->PUPDR = (regs->PUPDR & ~m_msk) | (pup << m_shift); regs->OTYPER = (regs->OTYPER & ~(1 << pos)) | (od << pos); - regs->OSPEEDR = (regs->OSPEEDR & ~m_msk) | (0x02 << m_shift); + regs->OSPEEDR = (regs->OSPEEDR & ~m_msk) | (STM_OSPEED << m_shift); } #define USB_BOOT_FLAG_ADDR (CONFIG_RAM_START + CONFIG_RAM_SIZE - 1024) diff --git a/src/stm32/stm32f1.c b/src/stm32/stm32f1.c index c0ae35fa..88500165 100644 --- a/src/stm32/stm32f1.c +++ b/src/stm32/stm32f1.c @@ -68,7 +68,6 @@ gpio_clock_enable(GPIO_TypeDef *regs) RCC->APB2ENR; } - static void stm32f1_alternative_remap(uint32_t mapr_mask, uint32_t mapr_value) { // The MAPR register is a mix of write only and r/w bits @@ -80,6 +79,8 @@ static void stm32f1_alternative_remap(uint32_t mapr_mask, uint32_t mapr_value) AFIO->MAPR = mapr; } +#define STM_OSPEED 0x1 // ~10Mhz at 50pF + // Set the mode and extended function of a pin void gpio_peripheral(uint32_t gpio, uint32_t mode, int pullup) @@ -94,20 +95,20 @@ gpio_peripheral(uint32_t gpio, uint32_t mode, int pullup) if (mode == GPIO_INPUT) { cfg = pullup ? 0x8 : 0x4; } else if (mode == GPIO_OUTPUT) { - cfg = 0x1; + cfg = STM_OSPEED; } else if (mode == (GPIO_OUTPUT | GPIO_OPEN_DRAIN)) { - cfg = 0x5; + cfg = 0x4 | STM_OSPEED; } else if (mode == GPIO_ANALOG) { cfg = 0x0; } else { if (mode & GPIO_OPEN_DRAIN) // Alternate function with open-drain mode - cfg = 0xd; + cfg = 0xc | STM_OSPEED; else if (pullup > 0) // Alternate function input pins use GPIO_INPUT mode on the stm32f1 cfg = 0x8; else - cfg = 0x9; + cfg = 0x8 | STM_OSPEED; } if (pos & 0x8) regs->CRH = (regs->CRH & ~msk) | (cfg << shift); diff --git a/src/stm32/stm32f4.c b/src/stm32/stm32f4.c index 06312832..6cbfd22a 100644 --- a/src/stm32/stm32f4.c +++ b/src/stm32/stm32f4.c @@ -68,6 +68,8 @@ gpio_clock_enable(GPIO_TypeDef *regs) RCC->AHB1ENR; } +#define STM_OSPEED 0x2 // ~50Mhz at 40pF on STM32F4 (~25Mhz at 40pF on STM32F2) + // Set the mode and extended function of a pin void gpio_peripheral(uint32_t gpio, uint32_t mode, int pullup) @@ -88,7 +90,7 @@ gpio_peripheral(uint32_t gpio, uint32_t mode, int pullup) regs->MODER = (regs->MODER & ~m_msk) | (mode_bits << m_shift); regs->PUPDR = (regs->PUPDR & ~m_msk) | (pup << m_shift); regs->OTYPER = (regs->OTYPER & ~(1 << pos)) | (od << pos); - regs->OSPEEDR = (regs->OSPEEDR & ~m_msk) | (0x02 << m_shift); + regs->OSPEEDR = (regs->OSPEEDR & ~m_msk) | (STM_OSPEED << m_shift); } #define USB_BOOT_FLAG_ADDR (CONFIG_RAM_START + CONFIG_RAM_SIZE - 4096) diff --git a/src/stm32/stm32h7.c b/src/stm32/stm32h7.c index c89dd9c5..f58154d7 100644 --- a/src/stm32/stm32h7.c +++ b/src/stm32/stm32h7.c @@ -102,6 +102,8 @@ gpio_clock_enable(GPIO_TypeDef *regs) enable_pclock((uint32_t)regs); } +#define STM_OSPEED 0x2 // ~85Mhz at 50pF + // Set the mode and extended function of a pin void gpio_peripheral(uint32_t gpio, uint32_t mode, int pullup) @@ -122,7 +124,7 @@ gpio_peripheral(uint32_t gpio, uint32_t mode, int pullup) regs->MODER = (regs->MODER & ~m_msk) | (mode_bits << m_shift); regs->PUPDR = (regs->PUPDR & ~m_msk) | (pup << m_shift); regs->OTYPER = (regs->OTYPER & ~(1 << pos)) | (od << pos); - regs->OSPEEDR = (regs->OSPEEDR & ~m_msk) | (0x02 << m_shift); + regs->OSPEEDR = (regs->OSPEEDR & ~m_msk) | (STM_OSPEED << m_shift); } #if !CONFIG_STM32_CLOCK_REF_INTERNAL |