#ifndef LIB_REG_GPIO_H #define LIB_REG_GPIO_H #include #define GPIOA_PDOR REG_32(0x400FF000) /* Port Data Output Register */ #define GPIOA_PSOR REG_32(0x400FF004) /* Port Set Output Register */ #define GPIOA_PCOR REG_32(0x400FF008) /* Port Clear Output Register */ #define GPIOA_PTOR REG_32(0x400FF00C) /* Port Toggle Output Register */ #define GPIOA_PDIR REG_32(0x400FF010) /* Port Data Input Register */ #define GPIOA_PDDR REG_32(0x400FF014) /* Port Data Direction Register */ #define GPIOB_PDOR REG_32(0x400FF040) /* Port Data Output Register */ #define GPIOB_PSOR REG_32(0x400FF044) /* Port Set Output Register */ #define GPIOB_PCOR REG_32(0x400FF048) /* Port Clear Output Register */ #define GPIOB_PTOR REG_32(0x400FF04C) /* Port Toggle Output Register */ #define GPIOB_PDIR REG_32(0x400FF050) /* Port Data Input Register */ #define GPIOB_PDDR REG_32(0x400FF054) /* Port Data Direction Register */ #define GPIOC_PDOR REG_32(0x400FF080) /* Port Data Output Register */ #define GPIOC_PSOR REG_32(0x400FF084) /* Port Set Output Register */ #define GPIOC_PCOR REG_32(0x400FF088) /* Port Clear Output Register */ #define GPIOC_PTOR REG_32(0x400FF08C) /* Port Toggle Output Register */ #define GPIOC_PDIR REG_32(0x400FF090) /* Port Data Input Register */ #define GPIOC_PDDR REG_32(0x400FF094) /* Port Data Direction Register */ #define GPIOD_PDOR REG_32(0x400FF0C0) /* Port Data Output Register */ #define GPIOD_PSOR REG_32(0x400FF0C4) /* Port Set Output Register */ #define GPIOD_PCOR REG_32(0x400FF0C8) /* Port Clear Output Register */ #define GPIOD_PTOR REG_32(0x400FF0CC) /* Port Toggle Output Register */ #define GPIOD_PDIR REG_32(0x400FF0D0) /* Port Data Input Register */ #define GPIOD_PDDR REG_32(0x400FF0D4) /* Port Data Direction Register */ #define GPIOE_PDOR REG_32(0x400FF100) /* Port Data Output Register */ #define GPIOE_PSOR REG_32(0x400FF104) /* Port Set Output Register */ #define GPIOE_PCOR REG_32(0x400FF108) /* Port Clear Output Register */ #define GPIOE_PTOR REG_32(0x400FF10C) /* Port Toggle Output Register */ #define GPIOE_PDIR REG_32(0x400FF110) /* Port Data Input Register */ #define GPIOE_PDDR REG_32(0x400FF114) /* Port Data Direction Register */ #endif /* LIB_REG_GPIO_H */